Embodiments of the present inventive concept relate to a correlated double sampling technology, and more particularly, to a correlated double sampling circuit amplifying and outputting a correlated double sampled signal, an image sensor including the same, and an image processing system including the image sensor.
In a CMOS image sensor (CIS), an operation of correlated double sampling (CDS) is needed. In addition, an image capture (or pickup) sensitivity adjustment function has become almost essential in the CIS.
In a conventional CIS, an image capture sensitivity of the CIS is adjusted, before performing analog to digital conversion on a result of a CDS operation, by adding a constant gain to a result of the CDS operation. In the conventional CIS, a programmable gain amplifier (PGA) circuit is embodied between a CDS circuit and an analog to digital converter (ADC). A conventional PGA circuit is a circuit including a plurality of capacitors having various capacitances and a result of CDS output from a CDS circuit is amplified by using each capacitance ratio of the plurality of capacitors. However, as the conventional PGA circuit is composed by using a plurality of capacitors, there may be occurred mismatch between capacitors. Additionally, in a general CIS, since ADC is connected to every column in a two dimensional pixel arrangement, adding a conventional PGA circuit to each column of the CIS increases a total area of the CIS.